The present invention relates in general to the testing of an integrated circuit designed within a semiconductor chip. In particular, the invention relates to routing scan chains in the semiconductor chip, to send test signals generated by a test pattern generator to test the integrated circuit within the semiconductor chip.
Scan chains are primarily used to transfer test signals during the process of testing an integrated circuit designed within a semiconductor chip. These scan chains use wiring connections to transfer the test signals to the required location of the integrated circuit within the semiconductor chip. The scan chains ensure that the process of testing the integrated circuit chips can be observed and controlled, such that the test signals can be routed to a desirable location within the semiconductor chip. The test pattern generator observes the signal responses at various locations of the integrated circuit. These generated responses correspond to the test signals. Further, these signal responses are analyzed for various errors that may result in the malfunctioning of the integrated circuit during its functional operation. The scan chains, by sending the test signals to the desired locations of the integrated circuits, significantly reduce the burden on the test pattern generator. Additionally, scan chains also help to reduce the overall testing time of the semiconductor chip.
The process of routing the scan chains is performed with care, so that the routing of critical signals by using scan chains is not adversely affected. Any adverse effect can result in congestion, impedance mismatching, electromagnetic interference, and negative impact on timing, for example, time delay, and the like. The level of complexity of a scan chain on a semiconductor chip depends on the integrated circuit on the semiconductor chip. The conventional hierarchical design for routing scan chains on a semiconductor chip with a group of processor resources arranged in tiled or multi-core manner is very complex. This is because each processor resource in the group of processor resources is connected at the top level, separately, through a set of scan chains, to the Input/Output (I/O) pins of the semiconductor chip. This makes the routes of scan chains lengthy and cumbersome, even for a semiconductor chip with a reasonably small number of processor resources. Further, these lengthy routes and cumbersome design create problems such as routing congestion at the top level, timing problems in critical paths, and the like. With an increase in the number of processor resources on the semiconductor chip, problems related to the routing of scan chains in it are amplified. Additionally, the complex design of the semiconductor chip makes time delay a significant problem. The time-delay problem becomes more significant when test signals need to be transferred to locations present in the middle of the semiconductor chip.
In light of the foregoing discussion, there is a need for a method and system for routing scan chains, to reduce the complexity of testing a semiconductor chip. Such a method and system would eliminate the problem of time delay in critical functional signals within the semiconductor chip. Further, the number of flops in the scan chains connecting the group of processor resources to transfer the test signals can be efficiently managed. Moreover, the semiconductor chip area would be efficiently utilized and would be scalable. As a result, the system could scale with the increase in the number of processor resources, if they are added to the system.